Two stage clock dejitter circuit for regenerating an E4 telecomm

Details Two stage clock dejitter circuit for regenerating an E4 telecomm Two stage clock dejitter circuit for regenerating an E4 telecomm

1994-07-08

1996-08-20

Ramirez, Ellis B.

Boots, shoes, and leggings

3701001, 370101, 375363, H04J 306

Patent

active

055485340

ABSTRACT:
A two stage desynchronizer is provided to receive a gapped data component of an STS-3C (STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO which receives the bytes, and a first FIFO read controller which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage of the desynchronizer includes a second FIFO, a FIFO fullness measurement block, and a VCXO. The FIFO fullness measurement block uses the incoming slightly gapped byte clock and the ungapped DS-4NA output clock as inputs for effectively measuring the relative fullness of the second FIFO, and provides a control signal based on the relative fullness. The control signal is fed to the voltage controlled crystal oscillator (VCXO) which generates the ungapped DS-4NA or E4 clock in response thereto.

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