Timing model and characterization system for logic simulation of

Details Timing model and characterization system for logic simulation of Timing model and characterization system for logic simulation of

1992-03-11

1996-08-20

Teska, Kevin J.

Boots, shoes, and leggings

364490, 364578, G06F 1710, G06F 1717

Patent

active

055485260

ABSTRACT:
A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value. The second formula also varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device.

REFERENCES:
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patent: 4924430 (1990-05-01), Zasio et al.
patent: 5095454 (1992-03-01), Huang
patent: 5231598 (1993-07-01), Vlahos
Dhimant Patel, "Charms: Characterization and Modeling System for Accurate Delay Prediction of ASIC Systems", IEEE 1990 Custom Integrated Circuit Conference, Paper 9.5.1.
An--Chang Deng, Piecewise-Linear Timing Delay Modeling for Digital CMOS Circuits, IEEE Transactions on Circuits and Systems, vol. 35, No. 10, Oct. 1988, pp. 1330-1334.
Delay Equations For Timing Analysis, IBM Technical Disclosure Bulletin, vol. 34, No. 1, Jun. 1991, pp. 186,187.

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