Error detection and correction memory system

Details Error detection and correction memory system Error detection and correction memory system

1990-12-17

1993-04-27

Atkinson, Charles E.

Excavating

371 401, G06F 1110

Patent

active

052068650

ABSTRACT:
Two or more memory arrays are coupled to two or more error detection and correction (EDAC). Each memory array has a plurality of memory devices each having a plurality of outputs. The outputs of each memory are divided among the EDACs such that no more than two outputs from a single memory device are coupled to a single EDAC.

REFERENCES:
patent: 4633472 (1986-12-01), Krol
patent: 4775978 (1988-10-01), Hartness
patent: 5056095 (1991-10-01), Horiguchi et al.

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