First arbiter coupled to a first bus receiving requests from dev

Details First arbiter coupled to a first bus receiving requests from dev First arbiter coupled to a first bus receiving requests from dev

1995-03-03

1997-01-21

Harvey, Jack B.

395290, 395729, G06F 1300

Patent

active

055967299

ABSTRACT:
An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

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82420/82430 PCI Set, ISA and EISA Bridges, Intel Corp., pp. 3-5, 17, 35, 37, 148, 154-157, 172-174, 211, 225-226, 293-302, 320-321, 345, 363-364, 438-444, 460-462 (1993).
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