Method of fabricating a metal gate MOS transistor with self-alig

Details Method of fabricating a metal gate MOS transistor with self-alig Method of fabricating a metal gate MOS transistor with self-alig

1994-08-31

1996-08-20

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 63, 437 69, 437 70, 437 72, H01L 2170, H01L 2700, H01L 21302, H01L 21304

Patent

active

055478956

ABSTRACT:
A method for manufacturing a CMOS transistor of integrated circuits having metal gates and self-aligned source and drain electrodes. The channel length can be precisely defined, and the leakage current can be reduced. Furthermore, the threshold voltage of the transistor can be increased by implanting impurities into the well or the substrate.

REFERENCES:
patent: 4078947 (1978-03-01), Johnson et al.
patent: 4282647 (1981-08-01), Richman
patent: 4766090 (1988-08-01), Coquin et al.
patent: 4994407 (1991-02-01), Custode et al.
patent: 5024961 (1991-06-01), Lee et al.
patent: 5270562 (1993-12-01), Wuidart
patent: 5382820 (1995-01-01), Yang et al.

Affiliated with

Also associated with

Rating

Method of fabricating a metal gate MOS transistor with self-alig does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a metal gate MOS transistor with self-alig, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a metal gate MOS transistor with self-alig will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2330484