Semiconductor memory device with internal self-refreshing

Static information storage and retrieval – Addressing – Counting

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365222, 365233, G11G 700

Patent

active

055965458

ABSTRACT:
A semiconductor memory device with internal self-refreshing is provided. The invented memory device has a programmable internal oscillator for controlling a self-refreshing time period. The internal oscillator obviates the need for an external signal for refreshing data stored in the device's memory cells. The pin-out configuration of the device is analogous to the pin-out configuration of an SRAM device, so that the invented device can replace an SRAM device on a circuit board. The self-refreshing time period is programmable to different time periods depending upon the intended use of the device for minimizing power consumption by the device. The oscillator provides an output pulse for incrementing an address counter which generates internal refreshing addresses and also activates a memory word line for memory cell refreshing. A comparator compares an external address and the internal refreshing address generated by the counter. If the internal address to be written is being refreshed, a timer counts down the refresh time period, before the data is written to the address. The maximum write delay time period is equal to the refresh time period. Data can be read from an internal address, when the address is being refreshed, so that there is no read time delay. The invented device has memory cells of a simple structure, analogous to the cell structure of a DRAM device, so that the device of the present invention has a relatively low cost of manufacture. Further, the memory cell structure enables the device to have substantially high storage capacity.

REFERENCES:
patent: 5033026 (1991-07-01), Tsujimoto
patent: 5315557 (1994-05-01), Kim et al.
patent: 5329490 (1994-07-01), Murotani
patent: 5453959 (1995-09-01), Sakuta et al.

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