Semiconductor memory device including circuitry for activating a

Details Semiconductor memory device including circuitry for activating a Semiconductor memory device including circuitry for activating a

1992-10-30

1997-01-21

Gossage, Glenn

Static information storage and retrieval

Addressing

Sync/clocking

365193, 36523002, 36523006, G11C 11407

Patent

active

055965431

ABSTRACT:
A semiconductor memory device includes random-access memory cells arranged as an integrated memory cell array, a plurality of bit lines for exchanging data with each of the memory cells, and a plurality of word lines intersecting with the bit lines. An accessing method is applied to an address multiplexed type device in which a column address for selecting a bit line and a row address for selecting a word line are obtained from a single circuit. In this device, the input order of the column and row addresses during a read cycle differs from that during a write cycle. One of the word lines of the device is made active and then inactive during an active period of a row address strobe signal thereby speeding up the read/write operation.

REFERENCES:
patent: 4507761 (1985-03-01), Graham
patent: 4750839 (1988-06-01), Wang et al.
patent: 4758987 (1988-07-01), Sakui
patent: 4787067 (1988-11-01), Takemae et al.
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 4951251 (1990-08-01), Yamaguchi

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