Process for forming an electrically programmable read-only memor

Fishing – trapping – and vermin destroying

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437 52, 437203, H01L 218247

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active

057054150

ABSTRACT:
A semiconductor device is formed having a floating gate memory cell (11) that has its channel region (33) oriented vertically with a portion of the channel region (33) that is not capacitively coupled to a floating gate (32). The memory cell (11) is less likely to be over-erased and may be programmed by source-side injection. The cell (11) may not need to be repaired after erasing. Less power may be consumed during programming compared to hot electron injection and Fowler-Nordheim tunneling.

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Pein, et al.; "Performance of the 3-D Sidewall Flash EPROM Cell;" IEDM; pp. 11-14 (1993), month unknown.
Naruke, et al.; "A New Flash-Erase EEPROM Cell With A Sidewall Select-Gate On Its Source Side;" IEDM; pp. 603-606 (1989), month unknown.

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