Decoder circuit of a semiconductor memory device

Details Decoder circuit of a semiconductor memory device Decoder circuit of a semiconductor memory device

1986-05-19

1988-03-08

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307463, 307468, H03K 19094, H03K 19096, H03K 19082

Patent

active

047301333

ABSTRACT:
A decoder circuit of a semiconductor memory device includes a plurality of logic gates each consisted by a load transistor and drive transistors generating a line selection signal corresponding to input address signals, and a power source control circuit for controlling the power source voltage supplied to the logic gate corresponding to a mode designation signal which is a normal mode signal or an all selection mode signal. According to the present invention, when the all selection mode signal is input to the power source control circuit, the all selection mode state of the decoder circuit is obtained by pulling down the power source voltage supplied to the logic gate.

REFERENCES:
patent: 3917958 (1978-11-01), Hatsukano

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