Input signal conditioning circuit

Details Input signal conditioning circuit Input signal conditioning circuit

1985-01-28

1988-03-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307290, 307268, 307510, 307520, H03K 1716, H03K 329, H03K 501, H03K 526

Patent

active

047301317

ABSTRACT:
An input signal is applied to first and second logic gates to produce a first output out-of-phase with the input signal and a second output in-phase with the input signal. The first and second outputs are applied to a set/reset flip-flop whose output is applied to a transition detector to produce pulses having a minimum width when the input signal changes level for longer than some predetermined period Tl. The first and second logic gates are designed to have asymmetrical responses whereby input pulses of either polarity having less than the predetermined width Tl are treated as "noise spikes", are effectively filtered from the system, and do not cause a change in the state of the set/reset flip-flop.

REFERENCES:
patent: 3950656 (1976-04-01), Sumida et al.
patent: 3953744 (1976-04-01), Kawagoe
patent: 4258272 (1981-03-01), Huang
patent: 4267465 (1981-05-01), Haug et al.
patent: 4286174 (1981-08-01), Dingwall
patent: 4314166 (1982-02-01), Bismarck
patent: 4374331 (1983-02-01), Yamamoto et al.
patent: 4595845 (1986-06-01), Briggs
patent: 4596939 (1986-06-01), Yamada

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