Method for fabricating a fully depleted lateral transistor

Details Method for fabricating a fully depleted lateral transistor Method for fabricating a fully depleted lateral transistor

1995-06-02

1997-01-21

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 26, 437 41, 148DIG126, H01L 218234

Patent

active

055959210

ABSTRACT:
The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 4628341 (1986-12-01), Thomas
patent: 4914051 (1990-04-01), Huie et al.
patent: 4989058 (1991-01-01), Colak et al.
patent: 5132235 (1992-07-01), Williams et al.
patent: 5306656 (1994-04-01), Williams et al.
Appels, et al., "Thin Layer High-Voltage Devices", Philips J. Res., vol. 35, No. 1, 1980, pp. 1-13.

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