Multi-port register implementations

Details Multi-port register implementations Multi-port register implementations

1983-03-10

1985-08-13

Popek, Joseph A.

Static information storage and retrieval

Addressing

365189, G11C 1140

Patent

active

045354286

ABSTRACT:
The present invention is especially directed towards a memory array which utilizes means for comparing the address inputs of word decoders in the system such that, when a compare occurs, selected ones of the word decoders are disabled to prevent a multiple read and selected higher order read heads are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder.

REFERENCES:
patent: 3801965 (1974-04-01), Keller et al.
patent: 3896417 (1975-07-01), Beecham
patent: 4078261 (1978-04-01), Millhollan et al.
patent: 4090258 (1978-05-01), Cricchi
patent: 4106109 (1978-08-01), Fassbender
patent: 4183095 (1980-01-01), Ward
patent: 4314164 (1982-02-01), Tin et al.

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