Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-05-06
2000-01-25
Nelms, David
Static information storage and retrieval
Addressing
Sync/clocking
36518908, 365208, 365 63, 365 68, G11C 800
Patent
active
060184922
ABSTRACT:
A semiconductor memory device is grouped into a plurality of flexible macro chips. Under the circumstances, a clock input first stage circuit is arranged in a first flexible macro chip to supply an internal reference clock signal and a first internal clock signal in response to an external reference clock signal. Further, a group of command input first stage circuits are collectively arranged in a second flexible macro chip different from the first flexible macro chip. In this event, the the first internal clock signal is directly supplied to the command input first stage circuits so as to input a command signal.
REFERENCES:
patent: 4866508 (1989-09-01), Eichelberger et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5446675 (1995-08-01), Yoshimura
"ISSCC95 / Session 14 / DRAM / Paper FA 14.6" IEEE International Solid-State Circuits Conference pp. 254-254 (1995).
Le Thong
NEC Corporation
Nelms David
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