Memory cell output driver

Details Memory cell output driver Memory cell output driver

1976-08-09

1977-08-23

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 300, G06F 504

Patent

active

040443353

ABSTRACT:
A buffered serial to parallel memory system uses an output driver which is semi-independently operated by separate control logic. Following conventional serial data input to a first buffer, the separate control logic responds to a predetermined signal to independently clear a second buffer, transfer the data from the first buffer to the second buffer and then clear the first buffer for further data input. The stored data in the second buffer is then used for output devices requiring parallel data output.

REFERENCES:
patent: 3090943 (1963-05-01), Lewis
patent: 3193802 (1965-07-01), Deerfield
patent: 3374467 (1968-03-01), Cast et al.
patent: 3417377 (1968-12-01), Vietor et al.
patent: 3465295 (1969-09-01), Witt et al.
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3742456 (1973-06-01), McFiggens et al.
patent: 3763480 (1973-10-01), Weimer
7080-Data Processing System Reference Manual, A-22-6560-1, 1962, pp. 2-7.
7621-Tape Control Unit Reference Manual, R23-9671, 1962, pp. 27-28.

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