Frame synchronization stabilizer

Multiplex communications – Wide area network – Packet switching

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375116, H04J 306

Patent

active

052280365

ABSTRACT:
A frame synchronization stabilizer for stabilizing frame synchronization of received data has a generation circuit for generating a reference pattern which is the same as a predetermined frame synchronization pattern contained in data being transmitted. The stabilizer further has a comparison circuit for comparing, bit by bit, a data pattern in a synchronization pattern area of each frame of the received data with the reference pattern from the generation circuit. The comparison circuit outputs a mismatch pulse each time when a mismatch bit is detected by the comparison, and outputs a match pulse each time when it is detected that the data pattern is fully matched with the reference pattern. The number of the mismatch pulses from the comparison circuit is counted by a first counter. The first counter outputs an out-of frame detection signal when a counted value exceeds a particular value and is reset based upon the match pulse from the comparison circuit.

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Patent Abstracts of Japan Publication No. JP59158168, dated Sep. 7, 1984.
Patent Abstracts of Japan Publication No. JP58215842, dated Dec. 15, 1983.

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