Multivalued ALU

Details Multivalued ALU Multivalued ALU

1991-03-05

1993-07-13

Mai, Tan V.

Boots, shoes, and leggings

365168, G06F 700, G06F 1500

Patent

active

052279936

ABSTRACT:
A multivalued Arithmetic Logic Unit (ALU) is composed of a multivalued signal source, a memory array, a selection array, an AND array and an output circuit. The multivalued signal source generates signals each of which represents a logic value of multivalued logic. The memory array is provided with an address line group for each and every function to be inplemented, each address line group comprising a number of address lines. Which multivalued logic signals will appear on the address lines of each address line group depends upon a program based on the truth table of the corresponding function. Any one of the plural address line groups is selected by the selection array, to which a signal designating the function to be implemented is applied. One address line in the selected address line group is selected by the AND array, which has an input signal applied thereto, and the logic value signal on the selected line is delivered via the output circuit.

REFERENCES:
patent: Re32401 (1987-04-01), Beilstein, Jr. et al.
patent: 3656117 (1972-04-01), Maley et al.
patent: 4327424 (1982-04-01), Wu
patent: 4404655 (1983-09-01), Naiff
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4809227 (1989-02-01), Suzuki et al.
Giuliani et al., "Bipolar Read Only Memory With Three State Cells", IBM Technical Disclosure Bulletin vol. 26, #6 pp. 2742-2744, Nov. 1983.

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