Polycyclic timing system and apparatus for pipelined computer op

Details Polycyclic timing system and apparatus for pipelined computer op Polycyclic timing system and apparatus for pipelined computer op

1993-04-26

1996-04-23

Kriess, Kevin A.

Boots, shoes, and leggings

3642705, 3642706, 3642707, 364DIG1, G06F 112

Patent

active

055111815

ABSTRACT:
A polycyclic timing system and an apparatus for pipelined computer operation comprises a master state machine and a slave state machine. The master state machine produces a plurality of control signals in response to a clock signal. The master state machine comprises an oscillator, a plurality of data storage elements, and a next state feedback network. The oscillator is used to produce a clock signal that triggers the storage elements. The next state feedback network determines the control signals to output based on the current output data storage elements using logic in the next state feedback network. The slave state machine receives the control signals and uses them to produce several asynchronous pulse streams. The slave state machine preferably comprises a plurality of pulse forming state machines and a plurality of pulse transmission amplifiers. Each of pulse forming state machine is an edge to pulse converter that produces at least one pulse in response to a control signal received from the master state machine.

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Joseph D. Greenfield, "Practical Digital Design Using ICs", John Wiley & Sons, 1977, pp. 135-139 and 158-194.

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