Speculative execution processor

Details Speculative execution processor Speculative execution processor

1992-11-16

1996-04-23

Teska, Kevin J.

Boots, shoes, and leggings

3642292, 3642319, 3642599, 3642613, 3642615, 3642624, 3642631, 364DIG1, G06F 930, G06F 938

Patent

active

055111726

ABSTRACT:
The present invention discloses a speculative execution processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored in its memory. The processor comprises an instruction type distinguishing device for distinguishing a type of a conditional branch instruction included in the unexecuted instruction sequence, the condition of the conditional branch instruction depending on another instruction, an instruction parallel-issuing device for issuing in parallel instructions included in a succeeding instruction sequence to be executed following the conditional branch instruction and/or instructions included in an instruction sequence to be executed after the branching to the executing units while whether or not to branch is not determined, a branching determining device for determining whether to branch when the another instruction is executed, and an execution result managing device for identifying whether the execution results of the instruction sequences are effective based on the determining results of the branching determining device.

REFERENCES:
patent: 5127091 (1992-06-01), Boufarah et al.
patent: 5151981 (1992-09-01), Westcott et al.
patent: 5197137 (1993-03-01), Kumar et al.
patent: 5201057 (1993-04-01), Uht
H. Dwyer "A Fast Instruction Dispatch Unit for Multiple and out-of-Sequence Issuances", EE-CEG-87-15.
An Extended Superscalar Processor Prototype Based on the SIMP (Single Instruction Stream/Multiple Instruction Pipelining) Architecture, Pub. in 1990.

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