Error correction circuit

Details Error correction circuit Error correction circuit

1984-09-06

1986-08-26

Fleming, Michael R.

Excavating

371 38, 371 39, G06F 1110

Patent

active

046086927

ABSTRACT:
An error correction circuit in which an error location polynomial is determined on the basis of the code word of the code of a double correction BCH symbol in Galois field GF(2.sup.m), thereby determining the error location and error pattern necessary for the error correction. The error correction circuit includes: (a) means for generating a syndrome S.sub.i (i being an integer) from the code word: (b) first and second means for holding S.sub.1 and S.sub.0 out of the syndromes outputted from the syndrome generating means; (c) means for effecting the following calculation on the basis of the syndrome generated by the syndrome generating means:

REFERENCES:
patent: 4142174 (1979-02-01), Chen et al.
patent: 4360916 (1982-11-01), Kustedjo
patent: 4498175 (1985-02-01), Nagumo
patent: 4509172 (1985-04-01), Chen
patent: 4556977 (1985-12-01), Olderdissen

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