Timing analysis of VLSI circuits

Details Timing analysis of VLSI circuits Timing analysis of VLSI circuits

1993-02-23

1995-10-10

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1750

Patent

active

054576385

ABSTRACT:
A computer-implemented process for doing timing analysis of a VLSI sequential circuit that includes false paths. It includes the steps of transforming the circuit into a functionally equivalent .delta. path disjoint circuit for a given delay value and propagating all inverters to primary inputs of the circuit and performing a multifault test on all primary input fanouts of a particular length consisting solely either of all zoroes or of all ones.

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"Automatic Synthesis and Technology Mapping of Combinational Logic" by R. A. Bergamaschi, IEEE 1988, pp. 466-469.
"Timing Optimization on Mapped Circuits" by Yoshikawa et al., IEEE 28th ACM/IEEE Design Automation Conf., 1991, pp. 112-117.
"Socrates: A System for Automatically Synthesizing and Optimizating Combinational Logic" by Gregory et al., IEEE 23rd Design Automation Conf., 1986, pp. 79-85.
"MIS: A Multiple-Level Logic Optimization System" by Brayton et al., IEEE Trans. Computer-Aided Design, vol. CAD-6, No. 6, Nov. 1987, pp. 1062-1081.

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