Method for store rounding and circuit therefor

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364748, G06F 738

Patent

active

055110169

ABSTRACT:
A method and circuit for store rounding a number wherein the guard bit and least significant bit of the number are selectively exchanged depending on the IEEE rounding mode to simplify the decision-making circuit. Zero detection logic is performed on the guard, round and sticky bit positions to determine if incrementing is required. An incrementer provided with the number and a guard bit, which may be the true guard bit or a predetermined constant value depending on the rounding mode, responds to the zero detection logic to increment the number from the guard bit position.

REFERENCES:
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4562553 (1985-12-01), Matterdi et al.
patent: 4758972 (1988-07-01), Frazier
patent: 4839846 (1989-06-01), Hirose et al.
patent: 4941120 (1990-07-01), Brown et al.
patent: 5235533 (1993-08-01), Sweedler
patent: 5257215 (1993-10-01), Poon
patent: 5258943 (1993-11-01), Gamez et al.
patent: 5404324 (1995-04-01), Colon-Bonet
patent: 5408426 (1995-04-01), Takewa et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for store rounding and circuit therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for store rounding and circuit therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for store rounding and circuit therefor will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2314506

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.