Boots – shoes – and leggings
Patent
1993-12-15
1996-04-23
Gossage, Glenn
Boots, shoes, and leggings
395449, 395467, 395469, 395471, 364DIG1, G06F 1200, G06F 1300
Patent
active
055109349
ABSTRACT:
A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.
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Brennan John
Ciavaglia Steve J.
Hsu Peter Y.
Huffman William A.
Rodman Paul
Gossage Glenn
Silicon Graphics Inc.
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