Circuitry and method for clamping a boost signal

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327328, 327332, 327170, H03K 301

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active

055107494

ABSTRACT:
A clamping circuit clamping a boost signal supplied on a boost line includes a p-channel MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. p-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented.

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patent: 5305260 (1994-04-01), Ninomiya
patent: 5329168 (1994-07-01), Sugibayashi et al.
"Dual-Operating-Voltage Scheme for a Single 5-V 16-Moit DRAM", M. Hariguchi et al., IEEE Journal of Solid State Circuit, vol. 23, No. 5, pp. 1128-1132 .

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