Digital data receiver including timing adjustment circuit

Details Digital data receiver including timing adjustment circuit Digital data receiver including timing adjustment circuit

1984-11-09

1986-03-18

Bookbinder, Marc E.

Pulse or digital communications

Repeaters

Testing

375111, 375118, H04L 710

Patent

active

045773343

ABSTRACT:
Digital Data receiving apparatus includes means for adjusting the timing of the sampling instants. A phase controlled oscillator (PCO 19) provides timing signals for sampling the received signal and is controlled, at the commencement of a received signal, by a timing initialization circuit (17) responsive to repetitive phase alterations in a training sequence. The timing initialization circuit (17) includes a plurality of Discrete Fourier Transform (DFT) circuits (23) responsive to frequencies dependent on the power spectral densities of the received signal, which received signal may be modulated at a normal rate or a fall-back rate. The DFT circuits (23) measure the correlation of locally-generated frequencies with the incoming samples for a predetermined number of such samples to produce a plurality of complex signals. A selector circuit (24) selects a pair of the complex signals dependent on the modulation rate. The provided pair of complex signals are multiplied in a complex conjugate multiplier (25) to produce a complex output signal which is fed to a phase segment detector (26) to provide a complex rotated signal. The complex rotated signal is converted in a phase-to-time-shift converter circuit (27) to a signal (m) for controlling the PCO 19.

REFERENCES:
patent: 3758870 (1973-09-01), Schmitt et al.
patent: 4039748 (1977-08-01), Caron et al.
patent: 4137427 (1979-01-01), Choquet et al.
patent: 4227252 (1980-10-01), Godard
patent: 4313202 (1982-01-01), Kameya
patent: 4458355 (1984-07-01), Motley et al.

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