Method for forming gigaohm load for BiCMOS process

Details Method for forming gigaohm load for BiCMOS process Method for forming gigaohm load for BiCMOS process

1994-09-02

1995-10-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 57, 437 59, 437 60, 437918, 148DIG136, H01L 21265

Patent

active

054570620

ABSTRACT:
An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

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