Method of making top floating-gate flash EEPROM structure

Details Method of making top floating-gate flash EEPROM structure Method of making top floating-gate flash EEPROM structure

1994-07-15

1995-10-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437978, H01L 218247, H01L 21266

Patent

active

054570611

ABSTRACT:
A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.

REFERENCES:
patent: 4868629 (1989-09-01), Eitan
patent: 5045488 (1991-09-01), Yeh
patent: 5049515 (1991-09-01), Tzeng
patent: 5061654 (1991-10-01), Shimizu et al.
patent: 5284786 (1994-02-01), Sethi
patent: 5293328 (1994-03-01), Amin et al.

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