Progressive scan video processor having common memories for vide

Details Progressive scan video processor having common memories for vide Progressive scan video processor having common memories for vide

1984-08-31

1986-03-18

Britton, Howard W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 21R, 358242, H04N 701, H04N 568

Patent

active

045772258

ABSTRACT:
A processor, for providing a double line-rate video signal comprising alternating received lines and interpolated lines, comprises a triad of memories. As each incoming video signal is stored in one of the three memories, the remaining two are read at double the write clock rate. An output circuit interleaves a non-interpolated time compressed line of video obtained from one of the two memories being read with a time-compressed line of video obtained by interpolation from both of the two memories being read to provide a processed video output signal. The write-one read-two memory organization enables concurrent interpolation and speed-up of the video signal thereby minimizing potential clock timing problems inherent in progressive scan systems of the type where interpolation is provided separately either before or after video speed-up.

REFERENCES:
patent: 3830971 (1974-08-01), van de Polder
patent: 4322750 (1982-03-01), Lord
patent: 4364090 (1982-12-01), Wendland
patent: 4400719 (1983-08-01), Powers
patent: 4415931 (1983-11-01), Dischert
patent: 4480267 (1984-10-01), van den Avoort
patent: 4484188 (1984-11-01), Ott
patent: 4539592 (1985-09-01), Tanaka

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