Dual word line, electrically alterable, nonvolatile floating gat

Details Dual word line, electrically alterable, nonvolatile floating gat Dual word line, electrically alterable, nonvolatile floating gat

1983-02-18

1986-03-18

Clawson, Jr., Joseph E.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 236, 357 54, 357 59, 357 67, 365185, H01L 2978

Patent

active

045772150

ABSTRACT:
A structure having dual word line, electrically alterable, nonvolatile floating gate memory cell is described wherein the word-line-to-floating gate capacitance is made significantly greater than either the program-line-to-floating gate capacitance or the floating-gate-to-substrate capacitance. This allows the program line and word line to be counter driven to minimize coupling to the floating gate during the write/erase cycle and to maximize coupling during the read cycle. The net result is higher write/erase/read efficiencies than heretofore possible.

REFERENCES:
patent: 3500142 (1970-03-01), Kahng
patent: 4099196 (1978-07-01), Simko
patent: 4282446 (1981-08-01), McElroy
patent: 4314265 (1982-02-01), Simko
patent: 4355375 (1982-10-01), Arakawa
patent: 4395724 (1983-07-01), Iwahashi et al.
patent: 4422092 (1983-12-01), Guterman
"16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage", W. S. Johnson et al., Electronics, Feb. 28, 1980, pp. 113-117.

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