Method of determining end of cleaning of semiconductor manufactu

Details Method of determining end of cleaning of semiconductor manufactu Method of determining end of cleaning of semiconductor manufactu

1988-11-30

1991-05-21

Chaudhuri, Olik

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

156626, 156643, 156644, H01L 21465, H01L 2166, B08B 700

Patent

active

050166638

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a method of determining an end of cleaning of a semiconductor manufacturing apparatus, which is adapted to determine an end of cleaning when the interior of a semiconductor substrate process chamber of a semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge.


BACKGROUND ART

Mass spectrometry, emission spectroscopy, and the like are known as methods of monitoring and end of cleaning when the interior of a reaction chamber (deposition chamber) of a plasma CVD (chemical vapor deposition) apparatus is cleaned by dry etching using plasma discharge. In addition, Japanese Patent Disclosure (Kokai) No. 61-145825 discloses a power measurement method of detecting an end of cleaning by measuring a reflecting power of a plasma discharge power or a bias voltage generated by a plasma electrode. According to a known time control method, a time for dry etching cleaning is controlled by estimating the total thickness of a film deposited in a reaction chamber from the thickness of a film deposited on a semiconductor substrate and calculating a cleaning time in accordance with the estimated total film thickness.
In the power measurement method, however, since the inductance and capacitance of a matching circuit inserted between a high-frequency power source and a discharge electrode is fixed at the start of cleaning, the inductance may be set in a mismatched state by the end of cleaning, and hence a plasma state becomes unstable. This worsens reproducibility of a cleaning process under the same conditions, and as a result, the time required for cleaning becomes long.
In the time control method, a deposition film thickness in the reaction chamber cannot be accurately measured, and overetching must be performed for a period of time longer than a calculated time by 40% or more in consideration of a variation in estimated total film thickness. For this reason, the operation efficiency of a plasma CVD apparatus is degraded, and the throughput of semiconductor substrates is decreased. In addition, since a carbon contamination layer is formed on an electrode surface during the long overetching operation described above because of the use of an etching gas (normally, a CF.sub.4 /O.sub.2 gas), the state of the reaction chamber becomes unstable. For this reason, in order to obtain uniformity within .+-.5% of the thickness of a plasma CVD film on a semiconductor substrate, a deposition process must be frequently performed on a dummy substrate to stabilize the state of the reaction chamber. This operation further decreases the operation efficiency and the throughput.


PROBLEMS TO BE SOLVED BY THE INVENTION

As described above, in the power measurement method, the problems are associated with the fact that the impedance is mismatched during cleaning. The problems posed in the time control method are associated with the fact that the operation efficiency of the semiconductor manufacturing apparatus is decreased. The present invention has been made in consideration of the above situation, and has as its object to provide a method of determining an end of cleaning of a semiconductor manufacturing apparatus, in which an end of cleaning can be determined with high precision in a real time manner, and the operation efficiency of the semiconductor manufacturing apparatus can be increased by shortening the time required for cleaning.


MEANS FOR SOLVING THE PROBLEMS

According to the present invention, a method of determining an end of cleaning of a semiconductor manufacturing apparatus is characterized in that when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, an impedance between discharge electrodes or a temperature in the semiconductor substrate process chamber is monitored while a constant current or voltage is supplied from a high-frequency power source to the discharge electrodes during plasma discharge an abrupt change in the impedance or temperatu

REFERENCES:
patent: 4207137 (1980-06-01), Tretola

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