Pipeline system with parallel data identification and delay of d

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36494834, 36496426, G06F 900

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049166590

ABSTRACT:
A pipeline system which is suitable for the processing of data accompanied by data identifying signals comprises interconnected modules which process the data and which controllably transfer the data to one another. Data processing in a module introduces a delay of the data. For correct data processing in a module, the data identifying signals must be in synchronism with the data. In a pipeline system in accordance with the invention, the data identifying signals are applied in parallel to all modules, these signals being delayed in a module by a delay means until the data whereto the signals relate have reached the relevant module. The foregoing has the advantage that the number of connections between the modules is reduced.

REFERENCES:
patent: 4210962 (1980-07-01), Marsh et al.
patent: 4507728 (1985-03-01), Sakamoro et al.
patent: 4574345 (1986-03-01), Kowesky
Shigeru Sasaki et al., "High Speed Pipeline Image Processor with a Modifiable Network", Proc. First International Conf. on Supercomputing Systems (St. Petersburg, Fla., Dec. 16-20, 1985), pp. 476-484.

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