Method and apparatus for a high performance round robin distribu

Details Method and apparatus for a high performance round robin distribu Method and apparatus for a high performance round robin distribu

1990-10-05

1993-08-31

Lee, Thomas C.

Boots, shoes, and leggings

395550, 395725, 3642292, 3642401, 3642404, 3642405, 3642427, 36424292, 3642717, 364DIG1, G06F 1337

Patent

active

052416291

ABSTRACT:
A multiprocessor system includes a plurality of identical central subsystem (CSS) units, a plurality of memory subsystem units and input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. Each CSS unit includes cycle stealer logic circuits which grant bus cycles on a round robin basis. The cycle stealer logic circuits are connected to receive high priority request signals from the network and refuse acceptance of a cycle granted to such CSS unit as a low priority requester thereby passing it along to a next lower priority CSS unit.

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