Logic path length reduction using boolean minimization

Details Logic path length reduction using boolean minimization Logic path length reduction using boolean minimization

1987-12-02

1990-04-10

Lall, Parshotam S.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

049166271

ABSTRACT:
An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

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