Patent
1988-09-13
1990-04-10
James, Andrew J.
357 65, 357 68, H01L 2348, H01L 2952
Patent
active
049165208
ABSTRACT:
There is disclosed a semiconductor device comprising a plurality of lower level interconnections having first, second and third lower level interconnections, an upper level interconnection connected to the first and second lower level interconnections and extending over the third lower level interconnection in spacing relationship, and at least one pier formed on a central portion of the upper surface of one of the first and second lower level interconnections, and the pier has a width less than that of aforesaid one of the first and second lower level interconnections and is covered in its entire surface with a film formed of the same material as of the upper level interconnection, so that a force applied for wafer separation is partially supported by the pier.
REFERENCES:
patent: 4308090 (1981-12-01), Te Velde et al.
patent: 4646126 (1987-02-01), Iizuka
patent: 4807002 (1989-02-01), Donzelli
Jackson, Jr. Jerome
James Andrew J.
NEC Corporation
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