Method for obtaining low interconnect resistance on a grooved su

Details Method for obtaining low interconnect resistance on a grooved su Method for obtaining low interconnect resistance on a grooved su

1989-04-07

1990-04-10

James, Andrew J.

357 55, 357 68, H01L 2978

Patent

active

049165097

ABSTRACT:
In accordance with the teachings of this invention, a novel electrical interconnect structure is taught, together with the process for forming this structure. In accodance with the teachings of this invention, this structure includes an electrical interconnect layer which is formed on a grooved portion of the surface of a semiconductor device. Thus, the effective cross-sectional area of the electrical interconnect layer is increased because the electrical interconnect material is formed into the grooves. With the thickness of the electrical interconnect layer thus increased as compared with the thickness of prior art electrical interconnect layers, the sheet resistance of the electrical interconnect layer of this invention is reduced over the sheet resistance of prior art electrical interconnect layers. With a lower sheet resistance, a given length of electrical interconnect can be formed of the same resistance as in the prior art with a smaller width. Alternatively, for a given length and a given width, an electrical interconnect can be fabricated in accordance with the teachings of this invention having a lower resistance than in the prior art.

REFERENCES:
patent: 4650544 (1987-03-01), Erb
Lu et al., IEEE Electron Device Letters, "A New Conduction Model for Polycrystalline Silicon Films", (Apr. 1981), vol. EDL-2, No. 4, pp. 95-98.
Crowder and Zirinsky, IEEE Journal of Solid-State Circuits, "um MOSFET VLSI Technology: Part VII-Metal Silicide Interconnection Technology-A Future Perspective", (Apr. 1979), vol. SC-14, No. 2, pp. 198-200.
Ghate, Physics Today, "Interconnections in VLSI", (Oct. 1986), pp. 58-66.
Zhang et al., "Self-Aligned Tantalum Silicide Process for VLSI Application", pp. 10-15, (best available citation).

Affiliated with

Also associated with

Rating

Method for obtaining low interconnect resistance on a grooved su does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for obtaining low interconnect resistance on a grooved su, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for obtaining low interconnect resistance on a grooved su will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2302440