Junction field effect transistor with vertical gate region

Details Junction field effect transistor with vertical gate region Junction field effect transistor with vertical gate region

1989-09-06

1990-04-10

Mintel, William

357 16, 357 58, 357 55, H01L 2980

Patent

active

049164996

ABSTRACT:
A junction field effect transistor having a source region, a gate region and a drain region, which are laminated to form a laminated layer, and a channel region formed on one side surface across the laminated layer, and also having a cavity which separates high impurity concentration regions of the source, gate and drain regions is disclosed. A method for manufacturing the above junction field effect transistor is also disclosed which has the steps of laminating semiconductor layers which become a source region, a gate region and a drain region, respectively, removing portions of the semiconductor layers other than portions which become an active region portion, and forming a channel region on one side surface across the laminated layers of the source region, gate region and drain region by the epitaxial growth method, and also forming cavities.

REFERENCES:
patent: 3823352 (1974-07-01), Pruniaux et al.
patent: 4259681 (1981-03-01), Nishizawa
patent: 4459605 (1984-07-01), Rice
patent: 4620207 (1986-10-01), Calviello
patent: 4636823 (1987-01-01), Margalit et al.

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