Pipeline computer with bypass route for returning data to reques

Details Pipeline computer with bypass route for returning data to reques Pipeline computer with bypass route for returning data to reques

1990-03-30

1992-11-10

Heckler, Thomas M.

Boots, shoes, and leggings

395425, 364DIG1, 3642318, 3642592, 3642394, G06F 938

Patent

active

051631571

ABSTRACT:
In a pipeline computer, a store sub-instruction address is stored into a most recent address register as well as into an address buffer in response to a store request and a load sub-instruction address is supplied to a main memory in response to a load sub-instruction. When a store sub-instruction data is stored into a buffer following the storage of the store sub-instruction address into the most recent address register, the contents of the address buffer and the data buffer are transferred to a location of the main memory specified by the sub-instruction address. Main memory data is retrieved from a location specified by an associated load sub-instruction address. A match or a mismatch is detected between the address in the most recent address register and an address generated in response to a subsequent load sub-instruction. If the latter occurs just prior to the storage of store sub-instruction data into the data buffer and if it accesses the same data as the store sub-instruction data, a match will be detected and data from an arithmetic logic unit is stored into a replay data register and returned to the request source. If a mismatch is detected and data read out of the main memory is passed through the reply data register to the request source.

REFERENCES:
patent: 4398245 (1983-08-01), Fujita
patent: 4561052 (1985-12-01), Tateno
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4794518 (1988-12-01), Mizushima
patent: 4916652 (1990-04-01), Schwarz et al.

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