Enhanced locked bus cycle control in a cache memory computer sys

Details Enhanced locked bus cycle control in a cache memory computer sys Enhanced locked bus cycle control in a cache memory computer sys

1990-11-03

1992-11-10

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 36424291, 364958, G06F 1206

Patent

active

051631431

ABSTRACT:
An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controlled 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.

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International Business Machines Corp., Supplements for the PS/2 Model 70 Technical Reference, Sep. 1988, pp. 3-20 and 3-21.

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