Computer system and method for setting recovery time upon execut

Details Computer system and method for setting recovery time upon execut Computer system and method for setting recovery time upon execut

1992-04-07

1992-11-10

Shaw, Dale M.

Boots, shoes, and leggings

3642842, 3642383, 3642715, 364DIG1, G06F 1314

Patent

active

051631350

ABSTRACT:
In a computer system, a CPU bus cycle control section receives a bus cycle request (BC-REQ) to generate a system bus cycle request (SBC-REQ) and feeds back a ready notice (READY-a) to the CPU. A system bus cycle control section performs the bus cycle control in response to the system bus cycle request (SBC-REQ) from the control section and generates a ready notice (READY-b) to the CPU bus cycle control section. The computer system includes a timer for delaying the ready notice (READY-b), a selector for selecting one of the ready notice (D'READY) delayed by the timer and the ready notice (READy-b) from the system bus cycle control section and supplies the selected ready notice to the CPU bus cycle control section and a register for holding access control information including a recovery state bit FRDY and recovery time data (RDY3-RDY0) of the timer.

REFERENCES:
patent: 4330826 (1982-05-01), Whiteside et al.
patent: 4451886 (1984-05-01), Guest et al.
patent: 4661905 (1987-04-01), Bomba et al.
patent: 4772888 (1988-09-01), Kimura
patent: 5065313 (1991-11-01), Lunsford

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