Multi-state EEprom read and write circuits and techniques

Details Multi-state EEprom read and write circuits and techniques Multi-state EEprom read and write circuits and techniques

1991-07-22

1992-11-10

Bowler, Alyssa H.

Static information storage and retrieval

Floating gate

Particular biasing

365201, 365104, 330 2, G11C 700, G11C 1600, G11C 2900

Patent

active

051630214

ABSTRACT:
Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.

REFERENCES:
patent: 4393475 (1983-07-01), Kitagawa et al.
patent: 4415992 (1983-11-01), Adloch
patent: 4799195 (1989-01-01), Iwahashi et al.
patent: 4807188 (1989-02-01), Casagrande
patent: 4956816 (1990-09-01), Atsumi et al.
patent: 4999813 (1991-03-01), Ohtsuka et al.

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