Branch processing unit with target cache using low/high banking

Details Branch processing unit with target cache using low/high banking Branch processing unit with target cache using low/high banking

1996-02-28

1998-03-24

Swann, Tod R.

395405, 395383, G06F 1200

Patent

active

057322430

ABSTRACT:
A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a prefetch block of 16 bytes) are separated into low and high block addresses (addressing split blocks of 8 bytes). The low and high block the low block address of an associated prefetch request may be designated may be allocated into either bank of the target cache (i.e., the low block of a prefetch request can start on an 8 byte alignment rather than the 16 byte alignment). For each prefetch request that includes both low and high block addresses, respective banks of the target cache are successively accessed based on the state of the bank select bit, such that the low block address is used to access one bank and the high block address is used to access the other bank.

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Ryan, Bob. "M1 Challenges Pentium", BYTE, pp. 83-87. Jan. 1994.

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