Fishing – trapping – and vermin destroying
Patent
1992-07-09
1993-08-31
Thomas, Tom
Fishing, trapping, and vermin destroying
437 49, 437979, 437985, H01L 21266, H01L 2176
Patent
active
052408701
ABSTRACT:
Two process flows are disclosed for the stacked etch fabrication of an EPROM array that utilizes cross-point cells with internal access transistors. In each process flow, the edges of the poly 1 floating gates parallel to the poly 2 word line are self-aligned to the word line, eliminating parasitic poly 2 transistors and process requirements for coping with such transistors.
REFERENCES:
patent: 4795719 (1989-01-01), Eitan
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4851365 (1989-07-01), Jeuch
patent: 4861730 (1989-08-01), Hsia et al.
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5013674 (1991-05-01), Bergemont
patent: 5028553 (1991-07-01), Esquivel et al.
Yosiaki S. Hisamune, et al.; A 3.6 .mu.m.sup.2 Memory Cell Structure for 16Mb EPROMS; IEEE 1989; Jul. 1989, pp. 583-586.
A. Bergemont, et al.; A High Performance CMOS Process for Submicron 16 Mb EPROM; IEEE 1989; Jul. 1989 pp. 591-594.
Yoichi Ohshima et al.; Process and Device Technologies for 16Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell; IEEE 1990; Apr. 1990 pp. 95-98.
Chaudhari C.
National Semiconductor Corporation
Thomas Tom
LandOfFree
Stacked gate process flow for cross-point EPROM with internal ac does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked gate process flow for cross-point EPROM with internal ac, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked gate process flow for cross-point EPROM with internal ac will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2297045