Stacked gate process flow for cross-point EPROM with internal ac

Fishing – trapping – and vermin destroying

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437 49, 437979, 437985, H01L 21266, H01L 2176

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active

052408701

ABSTRACT:
Two process flows are disclosed for the stacked etch fabrication of an EPROM array that utilizes cross-point cells with internal access transistors. In each process flow, the edges of the poly 1 floating gates parallel to the poly 2 word line are self-aligned to the word line, eliminating parasitic poly 2 transistors and process requirements for coping with such transistors.

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patent: 5028553 (1991-07-01), Esquivel et al.
Yosiaki S. Hisamune, et al.; A 3.6 .mu.m.sup.2 Memory Cell Structure for 16Mb EPROMS; IEEE 1989; Jul. 1989, pp. 583-586.
A. Bergemont, et al.; A High Performance CMOS Process for Submicron 16 Mb EPROM; IEEE 1989; Jul. 1989 pp. 591-594.
Yoichi Ohshima et al.; Process and Device Technologies for 16Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell; IEEE 1990; Apr. 1990 pp. 95-98.

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