Biasing arrangement for push-pull amplifier

Details Biasing arrangement for push-pull amplifier Biasing arrangement for push-pull amplifier

1976-03-16

1977-07-19

Mullins, James B.

Amplifiers

Modulator-demodulator-type amplifier

330 22, 330 24, 330 35, H03F 318

Patent

active

040371662

ABSTRACT:
A biasing arrangement comprising: a first transistor for driving a pair of field effect transistors (FET's) jointly forming a push-pull amplifier; a second transistor connected in series in the collector circuit of the first transistor, the voltage across the second transistor being applied as the gate-bias voltage for the FET's; and a constant current source connected to the base of the second transistor for causing a substantially constant current to flow through a resistor connected between the collector and base of the second transistor. With this arrangement, across the resistor is developed a stabilized sufficiently large voltage as compared with the base to emitter voltage of the second transistor. Thus, the gate bias voltages of the FET's are stabilized against the fluctuations of the ambient temperature.

REFERENCES:
patent: 3675142 (1972-07-01), Fichtner

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