Circuitry and methods for erasing EEPROM transistors

Details Circuitry and methods for erasing EEPROM transistors Circuitry and methods for erasing EEPROM transistors

1996-09-24

1998-03-24

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518526, 36518529, 36518533, 365218, G11C 1134, G11C 700

Patent

active

057320209

ABSTRACT:
Circuitry and methods for performing a global erase of an array of electrically-erasable programmable read-only memory (EEPROM) transistors are provided. The voltages used to erase the EEPROM transistors are controlled so that the maximum voltage across the gate oxide of previously erased transistors in the array does not exceed a predetermined maximum acceptable voltage level, thereby avoiding gate oxide damage due to high electric fields.

REFERENCES:
patent: 5428568 (1995-06-01), Kobayashi et al.
patent: 5491657 (1996-02-01), Haddad et al.
patent: 5625211 (1997-04-01), Kowshik

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