Integrated programmable logic array

Registers – Transfer mechanism – Traveling pawl

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Details

307207, 340166R, 340173AM, 364900, G11C 1500, H03K 1908

Patent

active

040370895

ABSTRACT:
An integrated circuit comprising a programmable logic array includes an AND-gate array and an OR-gate array connected thereto with column lines of the AND-gate array being shared in common with column lines of the OR-gate array. The AND-gate array and the OR-gate array are both operated dynamically, and a dynamically operated shift register is interconnected between an output of the OR-gate array and an input of the AND-gate array, to supply a feedback signal to the latter to realize sequential logic functions.

REFERENCES:
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 3656010 (1972-04-01), Huyben et al.
patent: 3761902 (1973-09-01), Weinberger
patent: 3816725 (1974-06-01), Greer
patent: 3924243 (1975-12-01), Vermeulen
Kent Andres, "Mos Programmable Logic Arrays," A Texas Instruments Application Report, No. CA-158, Oct. 1970, pp. 1-4.
J. E. Elliott et al., "Array Logic Processing," IBM Technical Disclosure Bulletin, vol. 16, No. 2, July 1973, pp. 586-587.

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