Minimal delay leading one detector with result bias control

Details Minimal delay leading one detector with result bias control Minimal delay leading one detector with result bias control

1992-06-09

1994-04-19

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

341 79, H03M 700

Patent

active

053049942

ABSTRACT:
A circuit and a method for providing an indication of the position of a bit having a selected characteristic in an n-bit binary word are disclosed. The n bits of the binary word are arranged into groups of W bits so that each group is input to a fundamental encoder. The position of the bit having the selected characteristic, among each group of W bits is provided as an encoded output. A multiplexer tree provides a single output indicative of the position of the bit having the selected characteristic in the binary word based on the encoded outputs from the encoders.

REFERENCES:
patent: 4677625 (1987-06-01), Betts et al.
patent: 5097261 (1992-03-01), Langdon, Jr. et al.
patent: 5115240 (1992-05-01), Fujiwara et al.
patent: 5144304 (1992-09-01), McMahon et al.
"Introduction to Arithmetic For Digital Systems Designers", Shlomo, Waser, pp. 119-123, ISBN 0-03-060571-7.
"Digital Computer Arithmetic-Design and Implementation" Cavanagh, Joseph, J. F., pp. 388, 391, ISBN 0-07-010282-1.

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