Stacked solid via formation in integrated circuit systems

Details Stacked solid via formation in integrated circuit systems Stacked solid via formation in integrated circuit systems

1991-01-07

1992-11-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437192, 437203, 437228, 437246, 437978, H01L 2144

Patent

active

051622602

ABSTRACT:
A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.

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