Method of producing capacitive element integrated circuit

Details Method of producing capacitive element integrated circuit Method of producing capacitive element integrated circuit

1992-04-03

1992-11-10

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 52, 437919, H01L 2170

Patent

active

051622530

ABSTRACT:
For a process of producing a capacitive element with a storage node electrode formed of layered electrode, there is proposed a method of preventing an unstable condition that a part of the storage node electrode during the processes is positioned in the air without support therebelow. The storage node electrode is formed by embedding a polysilicon plug in an aperture which reaches to a silicon active layer on a silicon substrate from the surface where a polysilicon capacitive electrode is formed on a polysilicon capacitive electrode provided thereon with the first capacitive insulating film. After a second capacitive insulating film and a polysilicon capacitive electrode are formed, the polysilicon capacitive electrodes are connected with each other by a polysilicon plug to form a cell plate electrode.

REFERENCES:
patent: 5006481 (1991-04-01), Cham et al.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M Drams", T. Ema, et al., 1988 IEEE International Electron Devices Meeting, pp. 592-595.
"A Spread Stacked Capacitor (SSC) Cell for 64MBIT Drams", S. Inoue, et al., 1989 IEEE International Electron Devices Meeting, pp. 31-34.

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