Self-aligned bipolar transistor using selective polysilicon grow

Details Self-aligned bipolar transistor using selective polysilicon grow Self-aligned bipolar transistor using selective polysilicon grow

1991-06-03

1992-11-10

Quach, T. N.

Fishing, trapping, and vermin destroying

437 90, 437162, 437193, 148DIG26, H01L 21328, H01L 21283

Patent

active

051622459

ABSTRACT:
A polysilicon self-aligned transistor has a polysilicon layer (24) with a cavity (30) formed therein. To form the polysilicon layer (24) with a cavity (30), a thin seed layer (14) is disposed over an epitaxial layer (11a). Dielectric layers (16, 18) are formed over the seed layer (14), and are subsequently etched to define the polysilicon layer (24) and the cavity (30). The cavity (30) is defined by a dielectric plug (22). The exposed seed layer (14) is used to selectively grow the polysilicon layer (24). Thereafter, the dielectric plug (22) is removed to form the cavity (30) through which the base (32) is implanted into the substrate (12) and the emitter (36) is formed.

REFERENCES:
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4693782 (1987-09-01), Kikuchi et al.
patent: 4800171 (1989-01-01), Iranmanesh et al.
patent: 4808555 (1989-02-01), Mauntel et al.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 421-435, 492-495.
Mieno, F., et al., "Novel Selective Poly-- . . . ", IEEE IEDM Tech. Digest, 1987, pp. 16-19.

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