Method and apparatus for verifying timing during simulation of d

Details Method and apparatus for verifying timing during simulation of d Method and apparatus for verifying timing during simulation of d

1989-05-25

1992-03-10

Lall, Parshotam S.

Boots, shoes, and leggings

364488, 371 23, G06F 1520, G06F 1560

Patent

active

050954547

ABSTRACT:
A digital circuit simulation method and apparatus provide for critical path timing analysis of digital circuitry using a hybrid path tracing method. The hybrid path tracing performs path tracing when, for example, simulation values change at designated inputs. The path tracing can employ the simulation values for eliminating blocked paths. During tracing, the method and apparatus determine the shortest and longest paths from each input or beginning point to each end point. The end points are typically storage elements such as latches, flip-flops or systems outputs at a high functional level. The critical path tracing analysis finds the shortest and longest paths from the beginning point to the end point and records and saves the violation history, if any, associated with those paths. A timing template allows the user to develop the necessary input stimuli, in a logical ordered format to test the timing behavior of the digital circuit to be designed. Special procedures are also available for enabling the iteration of stimuli to check the timing of a transparent latch-based design. The system thus provides as an output either a summary or detailed history of violations at selected levels within the circuit to be analyzed. User input enables the system to isolate upon particular portions of the circuitry for determining correct operation.

REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4907180 (1990-03-01), Smith
patent: 4916627 (1990-04-01), Hathaway
patent: 4924430 (1990-05-01), Zasio et al.

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