Patent
1997-05-14
1999-07-13
Lee, Thomas C.
395834, 395838, 395859, G06F 1300
Patent
active
059238984
ABSTRACT:
A memory controller having request queue and snoop tables is provided for functioning with bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The tables are compared to minimize and more efficiently institute snoop operations as a function of the presence or absence of the same listings in the tables. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.
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Genduso Thomas B.
Leung Wan L.
Bogdon Bernard D.
International Business Machines - Corporation
Lee Thomas C.
Smith Michael G.
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